1. Field of the Invention
The present invention relates to a driving circuit for driving a plasma display unit, and more specifically, to a driving circuit with low energy loss while charging or discharging a plasma display unit.
2. Description of the Prior Art
Plasma display panel (PDP) has the advantages of large screen size, flat and thin structure, wide viewing angle and low radiation. Therefore, they are rapidly capturing the large-scale display panel market of the future. Plasma display panels work by charging the PDP with high voltage and high frequency alternating current (AC) thereby activating electrical charges in the plasma. During this process, ultraviolet rays bombard the phosphor on the wall and emit light. The plasma display panel behaves like a capacitor with alternating voltages applied on two electrodes. When the two electrodes of the PDP are suddenly short-circuited or charged by high voltage, an instantaneous large current will be generated which will cause electromagnetic interference and a great loss of energy. In order to reduce the instantaneous current, the driving circuit of a traditional plasma display panel uses an inductor to resonate with a capacitor to slow down the charging and discharging process of the plasma display panel. However, these driving circuits are very complicated and costly.
Please refer to FIG. 1. FIG. 1 is a schematic circuit diagram of a single-sided driving circuit 10 of a prior art plasma display unit. The single-sided driving circuit 10 is used for driving a plasma display unit 14. The plasma display unit 14 is represented by an equivalent capacitor C.sub.L. The single-sided driving circuit 10 comprises a two-way switch 12, four transistors M1, M2, M5 and M6, two diodes D1 and D2, an inductor L, a high-capacity capacitor C1, and two DC power supplies V and V.sub.G. The two-way switch 12 comprises two transistors M3, M4 and two zener diodes ZD1 and ZD2 for limiting voltages.
Please refer to FIG. 2. FIG. 2 shows timing diagrams of various nodes of the single-sided driving circuit in FIG. 1. Diagram A shows the potential of the input node A of the two-way switch 12. Diagram B shows the potential of the output node B of the two-way switch 12. Diagram C shows the potential of the gate of the transistor M1. Diagram D shows the potential of the gate of the transistor M2. Diagram E shows the potential of the gate of the transistor M5. Diagram F shows the potential of the gate of the transistor M6. Vo is the potential of the output port to the plasma display unit 14. Io is the current flowing through the plasma display unit 14. Since the transistors M1 and M5 are PMOS, the transistor M1 or M5 will be conducted if the gate of the transistor M1 or M5 is connected to low voltage, otherwise, the transistor M1 or M5 will be switched off. Since the transistors M2 and M6 are NMOS, the transistor M2 or M6 will be conducted if the gate of the transistor M2 or M6 is connected to high voltage, otherwise, the transistors M2 and M6 will be switchedoff. The control procedure shown by the timing diagrams of FIG. 2 is as followed:
step 1: before the time period T1, the potential Vo of the plasma display unit 14 is 0V, the transistors M2, M6 are conducting, and the transistors M1, M5 are switched off; PA1 step 2: in the time period T1, the gate C of the transistor M1 and the gate D of transistor M2 will be applied with low voltage 22, thus the transistor M1 will be switched on and the transistor M2 will be switched off, the potential of node A will rise to V.sub.G for controlling the operation of the two-way switch 12, the potential of node B will rise to V/2. At this time, the inductor L will resonate with the plasma display unit 14, and the output potential Vo will subsequently be slowly charged to V; PA1 step 3: in the time period T2, the gate C of transistor M1 and the gate D of the transistor M2 will be applied with high voltage 24, thus the transistor M2 will conduct and the transistor M1 will be switched off, the potential of A will drop to 0 to control the two-way switch 12, and the potential of B will rise to V due to the resonance. At this time, the output potential Vo is still at V. Because the potential difference between the drain and source of the transistor M5 approximates 0V, the parasitic diode between the drain and source conducts. In the time period T2, the gate E of the transistor M5 is applied with low potential 26 so as to switch on the transistor M5 with zero potential difference between its source and drain; PA1 step 4: in the time period T3, the gate C of the transistor M1 and the gate D of the transistor M2 again drops to low potential 28 causing the transistor M1 to be switched on and the transistor M2 to be switched off, the potential of A to rise again with subsequent switching on of the two-way switch 12. This leads to the drop of the potential of node B to V/2 while the gate E of the transistor M5 is controlled at high potential to switch off the transistor M5. At this time, the inductor L starts to resonate with the plasma display unit 14, and the load capacitor C.sub.L will then be discharged slowly until the output potential Vo drops to 0V; PA1 step 5: in the time period T4, the gate C of transistor M1 and the gate D of the transistor M2 is raised to high potential to switch off the transistor M1 and switch on the transistor M2, the potential of A will then drop to 0 and will switch off the two-way switch 12. At this time, the output potential Vo is still at 0V and the potential of node B will drop to 0V due to resonance. Since the potential difference between the drain and source of the transistor M6 approximates 0V, the parasitic diode will conduct. Also, at this time, the gate F of the transistor M6 rises to high potential 30 resulting in conduction of the transistor M6 so as to switch on the transistor M6 at zero voltage difference; and PA1 step 6: repeat step 2 to step 5 for continuous charging and discharging the plasma display unit 14. PA1 step(1) switching off the first switch so that the current of the inductor flows through the plasma display unit and decreases the potential at the first end of the plasma display unit until the parasitic diode of the second switch is conducted, and then conducting the second switch so that it is switched on at zero voltage; PA1 step(2) switching off the fourth switch and conduct the third switch; PA1 step(3) utilizing the power supply to charge the plasma display unit and the inductor via the third and second switches until the current of the inductor reaches a predetermined value; PA1 step(4) switching off the second switch so that the current of the inductor flows through the plasma display unit and increases the potential at the first end of the plasma display unit until the parasitic diode of the first switch is conducted, and then conducting the first switch so that it is turned on at zero voltage; PA1 step(5) switching off the third switch and conduct the fourth switch; PA1 step(6) utilizing the power supply to charge the plasma display unit and the inductor via the first and fourth switches until the current of the inductor reaches a predetermined value; and PA1 step(7) repeating step(1) to step(6) to repeatedly charge the plasma display unit for sustaining the image signal display.
Because the inductor L and load capacitor C.sub.L of the single-sided driving circuit 10 form a resonance circuit, the energy stored in the inductor L and the load capacitor C.sub.L will be mutually exchanged. By switching on either the transistors M5 or M6 when the output potential Vo has reached V or 0 respectively, a great amount of energy consumed by charging and discharging the load capacitor C.sub.L can be saved. Since each of the transistors M5 and M6 conducts when the potential difference between its drain and source is 0, it is called switching at zero voltage.
Please refer to FIG. 3. FIG. 3 is a circuit diagram of a double-sided driving circuit 40 formed by the single-sided driving circuit 10 in FIG. 1. The double-sided driving circuit 40 comprises two single-sided driving circuits 10 electrically connected to the two ends of the plasma display unit 14 for sustaining the display of image signals through continuous charging and discharging of the plasma display unit 14 by driving the plasma inside the plasma display unit 14 back and forth. Each of the two-way switches 42 of the double-sided driving circuit 40 comprises a two-way switch 12, transistors M1, M2, and a DC power supply V.sub.G of the driving circuit 10 shown in FIG. 1. The switches Qa and Qb comprise transistors M5 and M6. Because the double-sided driving circuit 40 has quite complicated components and requires the use of high-capacity capacitors C1, the double-sided driving circuit 40 is difficult to control and costly.